#include "cpu_info.h"
#include "asm_inline.h"

enum LEAF1_ECX {
    SSE3 = 1<<0,
    PCLMULQDQ = 1<<1,
    DTES64 = 1<<2,
    MONITOR = 1<<3,
    DS_CPL = 1<<4,
    VMX = 1<<5,
    SMX = 1<<6,
    EIST = 1<<7, // Intel ?
    TM2 = 1<<8,
    SSSE3 = 1<<9,
    L1_CONTEXT_ID = 1<<10,
    DEBUG_INTERFACE = 1<<11,
    FMA = 1<<12,
    CMPXCHG16B = 1<<13,
    XTPR_UPDATE_CONTROL = 1<<14,
    PERF_CAPABILITIES = 1<<15,
    // Reserved
    PCID = 1<<17,
    DCA = 1<<18,
    SSE4_1 = 1<<19,
    SSE4_2 = 1<<20,
    X2APIC = 1<<21,
    MOVBE = 1<<22,
    POPCNT = 1<<23,
    TSC_DEADLINE = 1<<24,
    AESNI = 1<<25,
    XSAVE = 1<<26,
    OSXSAVE = 1<<27,
    AVX = 1<<28,
    F16C = 1<<29,
    RDRAND = 1<<30
};

enum LEAF1_EDX {
    FPU = 1<<0,
    VME = 1<<1,
    DE = 1<<2,
    PSE = 1<<3,
    TSC = 1<<4,
    MSR = 1<<5,
    PAE = 1<<6,
    MCE = 1<<7,
    CMPXCHG8B = 1<<8,
    APIC = 1<<9,
    // Reserved
    SEP = 1<<11,
    MTRR = 1<<12,
    PGE = 1<<13,
    MCA = 1<<14,
    CMOV = 1<<15,
    PAT = 1<<16,
    PSE_36 = 1<<17,
    PSN = 1<<18,
    CLFLUSH = 1<<19,
    // Reserved
    DS = 1<<21,
    ACPI = 1<<22,
    MMX = 1<<23,
    FXSR = 1<<24,
    SSE = 1<<25,
    SSE2 = 1<<26,
    SELF_SNOOP = 1<<27,
    HTT = 1<<28,
    TM = 1<<29,
    // Reserved
    PBE = 1<<31,
};

cpu_info info;

void init_cpu_info()
{
    uint32_t rax, rbx, rcx, rdx;
    cpuid(1, 0, &rax, &rbx, &rcx, &rdx);

    info.FPU = (rcx & FPU) == 1;
    info.ACPI = (rcx & ACPI) == 1;
    info.MMX = (rcx & MMX) == 1;
    info.SSE = (rcx & SSE) == 1;
    info.SSE2 = (rcx & SSE2) == 1;

    info.SSE3 = (rdx & SSE3) == 1;
    info.SSSE3 = (rdx & SSSE3) == 1;
    info.SSE41 = (rdx & SSE4_1) == 1;
    info.SSE42 = (rdx & SSE4_2) == 1;
    info.VMX = (rdx & VMX) == 1;
    info.FMA = (rdx & FMA) == 1;
    info.AVX = (rdx & AVX) == 1;
}

const cpu_info* get_cpu_info()
{
    return &info;
}